This application is based on Japanese Patent Applications No. 11-308362, No. 11-366682, No. 11-366684, No. 2000-027384, No. 2000-027386, No. 2000-092473 and No. 2000-096540, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a thin film electronic device and a circuit board mounted with the same. More particularly, the invention relates to a thin film electronic device serving as a thin film capacitor, a thin film inductor, a thin film filter or the like for high-frequency applications, and to a circuit board mounted with the thin film electronic device.
2. Description of Prior Art
With a recent trend toward size reduction and performance enhancement of electronic systems, electronic components to be provided in such electronic systems have increasingly been demanded to have a smaller size, a thinner thickness and an improved performance for high-frequency applications. Particularly in the case of high-speed digital circuits for computers, even for personal computers, which are required to process a greater amount of information at a higher speed, the processing speeds have been increased with a clock frequency (operating) of 200 MHz to 1 GHz in CPU chips and a clock frequency of 75 MHz to 133 MHz on inter-chip buses.
In the case of LSIs, a source voltage is generally reduced for reduction of power consumption, as the integration degree is increased with a greater number of elements integrated in a chip. For circuits having a higher operating speed, a higher integration density and a lower operating voltage, it is essential that a passive element such as a capacitor has a smaller size and a greater capacity and exhibit excellent characteristics for high-frequency or high-speed pulses.
As the operating frequency of a logic circuit is increased, the resistance and inductance of an element tend to cause an instantaneous source voltage drop and an additional voltage noise in the logic circuit. This may result in an error on the logic circuit. An instantaneous source voltage drop occurring when logic circuits are simultaneously switched, for example, can be suppressed by instantaneous supply of energy accumulated in a capacitor. The capacitor to be used for this purpose is called xe2x80x9cdecoupling capacitorxe2x80x9d. The decoupling capacitor should be capable of supplying a current as soon as possible in response to current fluctuations occurring faster than the clock frequency in a loaded portion. Therefore, the decoupling capacitor should assuredly be operative in a frequency range between 100 MHz and 1 GHz. For this reason, a consideration has been given to the electrode structure of the capacitor for reduction in the impedance of the capacitor attributable to the inductance of a capacitor element which is liable to increase with the frequency.
Severer requirements are imposed not only on the electrical characteristics of the passive element per se but also on mounting characteristics (mounting accuracy and mounting reliability), for example, for improvement of mounting accuracy with a greater number of integrated elements and for improvement of reflow resistance in mounting a component.
For reduction in the inductance of contacts of a capacitor, U.S. Pat. No. 4,439,813 proposes a capacitor having a construction such that a via-hole is provided as extending through a dielectric layer, a top electrode layer and a protective layer for obtaining an electrical signal from a bottom electrode through the shortest distance and an external terminal of a solder bump is provided in the via-hole.
FIG. 1 illustrates the capacitor disclosed in this publication. A bottom electrode layer 33, an insulating layer 35, a top electrode layer 37 and a protective layer 39 are sequentially stacked on a carrier substrate 31. An external terminal 42 is connected to the bottom electrode layer 33 through a via-hole formed in the protective layer 39, and an external terminal 44 is connected to the top electrode layer 37 through another via-hole formed in the protective layer 39. The external terminal 44 is formed on the insulating layer 35.
In this capacitor, the external terminal 44 connected to the top electrode layer 37 is formed on the insulating layer 35, so that an excessive stress is exerted on the insulating layer 35 due to shrinkage of a solder bump in a reflow process. As a result, cracks are liable to develop in the insulating layer 35, making it difficult to provide for reliable insulation.
The external terminal 44 connected to the top electrode layer 37 is bonded to the carrier substrate 31 via the top electrode layer 37, the insulating layer 35 and the bottom electrode layer 33. Therefore, the external terminal 44 has a smaller bonding strength with respect to the carrier substrate 31. Hence, the external terminal 44 is liable to be dislodged when some shock is given thereto.
U.S. Pat. No. 4,439,813 also proposes a capacitor having a construction such that a via-hole is provided as extending through a dielectric layer, a top electrode layer and a protective layer for obtaining an electrical signal from a bottom electrode through the shortest distance and an external terminal of a solder bump is provided on a laminate metallurgy layer of Cr/Cu/Au (hereinafter referred to as xe2x80x9cBLM layerxe2x80x9d) formed on the interior surface of the via-hole.
FIG. 2 illustrates the proposed capacitor. A bottom electrode layer 33, an insulating layer 35, a top electrode layer 37 and a protective layer 39 are sequentially stacked on a carrier substrate 31. A via-hole 40 is formed in the protective layer 39, and a BLM layer 41 is provided on the interior surface of the via-hole 40. An external terminal 42 is connected to the BLM layer 41. An external terminal 44 is connected to the top electrode layer 37 through a via-hole 40 formed in the protective layer 39 and the BLM layer 41. The external terminal 44 is formed on the insulating layer 35.
The device reliability and mounting reliability of the capacitor are influenced by the thickness and covering property of the BLM layer 41 on which the external terminals 42, 44 are provided. In the capacitor of FIG. 2, a flat step 47 is provided around a vertically middle portion of the protective layer 39 on the interior surface of the via-hole 40 which accommodates the external terminal 42 connected to the bottom electrode layer 33. In the presence of the flat step 47, an edge 49 projects in the via-hole 40. Internal stresses in the BLM layer 41 are concentrated on the edge 49, so that cracks are liable to develop in the BLM layer 41. If the development of the cracks occurs, a solder may be diffused through the cracks, and the bonding strength between the interior surface of the via-hole 40 and the external terminal 42 maybe deteriorated. As a result, the device reliability and the mounting reliability may be reduced, i.e., the bottom face of the external terminal 42 may be separated from the electrode connected to the bottom face.
A conceivable approach to the prevention of the development of the cracks is to increase the thickness of the BLM layer 41. In this case, however, internal stresses in the BLM layer 41 are increased, presenting another problem of an adhesion failure such as separation of the BLM layer.
It is a principal object of the present invention to provide a thin film electronic device which features prevention of development of cracks in an insulating layer for reliable insulation.
It is another object of the invention to provide a thin film electronic device which features an improved bonding strength between external terminals and a carrier substrate.
It is further another object of the invention to provide a thin film electronic device which features a reduced inductance at contacts of external terminals and an improved bonding strength of the external terminals.
It is still another object of the invention to provide a circuit board mounted with any of the aforesaid thin film electronic devices.
In accordance with the present invention, there is provided a thin film electronic device which comprises: a carrier substrate; a laminate provided on the carrier substrate, and comprising a laminate structure having an insulating layer and a plurality of electrode layers, and a plurality of areas formed with no insulating layer; a thin film element formed in the laminate with the insulating layer held between the electrode layers; and a plurality of terminal electrodes electrically connected to the corresponding electrode layers and provided in the areas formed with no insulating layer for receiving electrical signals of different polarities applied thereto.